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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Description
The GLT5640L16 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 1,048,576 x 16 x 4 (word x bit x bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture and clock frequency up to 183MHz. All input and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII.
Features
* Single 3.3V ((0.3V) power supply
* High speed clock cycle time -5.5:183MHz<3-3-3>,-6:166MHz<3-3-3>, -7:143MHz<3-3-3>, -8: 125MHz<3-3-3> -10 : 100MHz<3-3-3> * Fully synchronous operation referenced to clock rising edge * Possible to assert random column access in every cycle * Quad internal banks controlled by BA0 & BA1 (Bank Select) * Byte control by LDQM and UDQM * Programmable Wrap sequence (Sequential / Interleave) * Programmable burst length (1, 2, 4, 8 and full page) * Programmable /CAS latency (2 and 3) * Automatic precharge and controlled precharge * CBR (Auto) refresh and self refresh * X16 organization * LVTTL compatible inputs and outputs * 4,096 refresh cycles / 64ms * Burst termination by Burst stop and Precharge command
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Pin Configurations
GLT5640L16
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
Pin Descriptions
Pin Name CLK CKE CS RAS CAS WE DQ0 ~ DQ15 Master Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data I/O Function Pin Name DQM A0-11 BA0,1 VDD VDDQ VSS VSSQ Function DQ Mask Enable Address Input Bank Address Power Supply Power Supply for DQ Ground Ground for DQ
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Block Diagram
CLK CKE
Clock Generator
Address
Mode Register
Row Address Buffer & Burst counter Bank D Bank C Bank B
Row Decoder
Bank A
CS RAS CAS WE
Column Address Buffer & Burst counter
Sense amplifier Column Decoder & Latch Circuoit
Command Decoder
DQM
Input & Output Buffer Latch Circuit
Control Logic
Data Control Circuit
DQ
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Pin Function
Symbol CLK CKE Input Input Input Function Master Clock: Other inputs signals are referenced to the CLK rising edge Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). Chip Select: CS enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. RAS , CAS , WE A0 - A13 Input Command Inputs: RAS , CAS and WE (along with CS ) define the command being entered. Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. The row address is specified by A0-A11. The column address is specified by A0-A7 Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Din Mask / Output Disable : When DQM is high in burst write, Din for the current cycle is masked. When DQM is high in burst read, Dout is disable (two - clock latency). Data Input / Output: Data bus Power Supply for the memory array and peripheral circuitry Power Supply are supplied to the output buffers only
CS
Input
Input
BA0,BA1 DQM, UDQM , LDQM DQ0 - DQ15 VDD, VSS VDDQ, VSSQ
Input Input I/O Supply Supply
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Absolute Maximum Ratings
Parameter Supply Voltage Supply Voltage for Output Input Voltage Output Voltage Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VDD VDDQ VI VO IO PD TOPT TSTG Conditions with respect to VSS with respect to VSSQ with respect to VSS with respect to VSSQ Ta = 25 C Value -0.5 to 4.6 -0.5 to 4.6 -0.5 to VDD+0.5 -0.5 to VDDQ+0.5 50 1 0 to 70 -65 to 150 Unit V V V V mA W C C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions (Ta = 0 ~ 70 C, unless otherwise noted)
Parameter Supply Voltage Supply Voltage for DQ Ground Ground for DQ High Level Input Voltage (all inputs) Low Level Input Voltage (all inputs) Symbol VDD VDDQ VSS VSSQ VIH VIL Min. 3.0 3.0 0 0 2.0 -0.3 Limits Typ. 3.3 3.3 0 0 Unit Max. 3.6 3.6 0 0 VDD + 0.3 0.8 V V V V V V
Note : 1.All voltages are referenced to Vss = 0V. 2.VIH (max) is acceptable 5.6V AC pulse width with 3ns of duration. 3.VIL (min) is acceptable -2.0V AC pulse width with 3ns of duration.
Pin Capacitance (Ta = 0 ~ 70C, VDD = VDDQ = 3.30.3V , VSS = VSSQ = 0V, unless otherwise noted)
Parameter Input Capacitance, address & control pin Input Capacitance, CLK pin Data input / output capacitance Symbol CIN CCLK CI/O Min 2.5 2.5 4.0 Max 3.8 3.5 6.5 Unit pF pF pF
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
DC Characteristics 1
(Ta = 0 ~ 70C, VDD = VDDQ = 3.30.3V, VSS = VSSQ = 0V, Output Open, unless otherwise noted)
Parameter Operating current Symbol ICC1 Test Conditions One bank active tRC = tRC(MIN), tCLK = tCLK(MIN), BL = 1, CL=3 CKEVIL(MAX), tCK = 15ns CKEVIL(MAX), CLKVIL(MAX) CS VDD - 0.2V tCK = 15ns, CKEVIH(MIN) CS VDD - 0.2V CLKVIL(MAX), CKEVIH(MIN)
All input signals are stable.
-5.5 100 2 1 20
-6 95 2 1 20
Limits (max.) -7 -8 85 2 1 20 85 2 1 20
Unit -10
Notes 1
85 2 1 20
mA mA mA 2
Precharge standby current in power down mode Precharge standby current in non power down mode
ICC2P ICC2PS ICC2N ICC2NS
20 7 5 35 35
20 7 5 35 35
20 7 5 35 35
20 7 5 35 35
20 7 5 35 35
mA mA mA 2
Active standby current in power down mode Active standby current in Nonpower down mode
ICC3P ICC3PS ICC3N ICC3NS
CKEVIL(MAX), tCK = 10ns CKEVIL(MAX), CLKVIL(MAX) CS VDD - 0.2V tCK = 15ns, CKEVIH(MIN) CS VDD - 0.2V CLKVIL(MAX), CKEVIH(MIN)
All input signals are stable.
mA
Operating current (Burst mode) Refresh current Self refresh current
NOTES
ICC4
ICC5 ICC6
All banks active tCK = tCK(MIN), BL=4, CL=3 All banks active tRC = tRC(MIN), tCLK = tCLK(MIN) CKE0.2V GLT5640L16 GLT5640L16L
140 160 1 0.5
130 150 1 0.5
100 130 1 0.5
80 110 1 0.5
80 110 1 0.5
mA mA mA mA
3 4
1. ICC(max) is specified at the output open condition. 2. Input signals are changed one time during 30ns. 3. Normal version: GLT5640L16 4. Low power version: GLT5640L16L
DC Characteristics 2 (Ta = 0 ~ 70C, VDD = VDDQ = 3.30.3V , VSS = VSSQ = 0V, unless otherwise noted)
Parameter Input leakage current (Inputs) Output leakage current (I/O pins) High level output voltage Low level output voltage Symbol II (L) IO (L) VOH VOL Test Condition 0VINVDD(MAX) Pins not under test = 0V 0VOUTVDD(MAX) DQ# in H - Z., DOUT is disabled IOH = -2mA IOL = 2mA Min 5 5 2.4 0.4 Max 5 5 Unit uA uA V V
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
AC Characteristics (Ta = 0 ~ 70C, VDD = VDDQ = 3.30.3V , VSS = VSSQ = 0V, unless otherwise noted) Test Conditions
AC input Levels (VIH/VIL) Input rise and fall time 2.0 / 0.8V 1ns Input timing reference level / Output timing reference level Output load condition 1.4V 50pF
Note): 1.if clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter.
Output Load Conditions
VDDQ V
OUT Z = 50 Device Under Test
VDDQ
50PF
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Switching Characteristics (Ta = 0 ~ 70C, VDD = VDDQ = 3.30.3V , VSS = VSSQ = 0V, unless otherwise noted)
Parameter CLK cycle time CL=3 CL=2 Symbol tCK3 tCK2 tCH tCL tT tIS tIH tRC tRFC tRCD tRAS tRP tWR tRRD tRSC tDAL tREF 5.5 Min Max 5.5 7 2.3 2.3 1 10 1.5 1 55 55 16.5 38.5 100k 15 11 11 2 4 64 -6 Min 6 8 2.5 2.5 1 1.5 1 60 60 18 42 15 12 12 2 4 Max Limits -7 Min Max 7 9 2.5 2.5 1 10 1.5 1 63 70 20 45 100k 15 14 14 2 4 64 -8 Min 8 10 3 3 1 1.5 1 70 80 20 48 20 20 20 2 4 Max -10 Min Max 10 13 3.5 3.5 1 10 2.5 1 90 100 30 60 100k 30 30 30 2 4 64 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCK tCK ms Note
CLK high pulse width CLK low pulse width Transition time of CLK Input Setup time Input Hold time Row Cycle Time Refresh Cycle Time Row to Column Delay Row active time Row Precharge time Write Recovery time Act to Delay time Mode Register Set Cycle time Data-in to ACTIVE command Refresh Interval time
10
10
1 2
100k
100k
3
64
64
Note : 1. tIS = tCKS (CKE setup time) , tCMS (Command setup time) , tAS (Address setup time) , tDS (Input data setup time). 2. tIH = tCKH (CKE hold time) , tCMH (Command hold time) , tAH (Address hold time) , tDH (Input data hold time). 3. tWR is so called tDPL.
Switching Characteristics (Ta = 0 ~ 70C, VDD = VDDQ = 3.30.3V , VSS = VSSQ = 0V, unless otherwise noted)
Parameter Access time from CLK CL = 3 CL = 2 Output Hold time from CLK CL = 3 CL = 2 Delay time , output low-impedance from CLK Delay time , output high-impedance from LCK Symbol tAC3 tAC2 tCH3 tCH2 tOLZ tOHZ -5.5 Min Max 5 6 2 2 0 2 5 -6 Min Max 5 6 Limits -7 Min Max 5.5 6 2.7 2.7 0 2.7 5.5 -8 Min Max 6 6 -10 Min Max 7 6 3 3 0 3 6 Unit ns ns ns ns ns ns Note *1 *1 *1 *1
2.5 2.5 0 2.5 5
3 3 0 3 6
Note : 1. If clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter.
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Basic Features and Function Description
1. Simplified State Diagram
Self
Refresh
en t ry F ex it
L SE
F
Mode Register Set
MRS
IDLE
L SE
REF
AUTO Refresh
CK E
C KE
ROW ACTIVE
BS T
A CT
Power Down
CKE CKE
T BS
Active Power Down
W (W rite rite re covery)
W
W to rit e w p re i dh th a rg e
e ri t
R
th wi arge ad ch Re Pre o Aut P RE
ea d
Au
e rit W
y er ov c re
Read
WRITE SUSPEND
CKE CKE
WRITE
Read (write recovery) Write
R Au t ead w o Pr i e c h th a rge
READ
CKE CKE
READ SUSPEND
W rite w ith Auto Precharge
(w ri
te re
it w h a rg e r te Wi Prech to Au
co v e ry )
Read with Auto Precharge
n)
PR E (P r
WRITE A SUSPEND
WRITE A
na t io
CKE CKE
CKE READ A CKE
READA SUSPEND
POW ER ON
Precharge
Precharge
Automatic sequence Manual input Note: After the AUTO refresh operation, precharge operation is performed automatically and enter the IDLE state
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PR E
(P r
e ch
-9-
ar
ge )
te r i on na t mi
mi te r
ar e ch ge
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
2.Truth Table
2.1 Command Truth Table
FUNCTION Device deselect No operation Mode register set Bank activate Read Read with auto precharge Write Write with auto precharge Precharge select bank Precharge all banks Burst stop CBR (Auto) refresh Self refresh Symbol DESL NOP MRS ACT READ READA WRIT WRITA PRE PALL BST REF SELF CKE n-1 H H H H H H H H H H H H H n X X X X X X X X X X X H L CS H L L L L L L L L L L L L RAS X H L L H H H H L L H L L CAS X H L H L L L L H H H L L WE X H L H H H L L L L L H H BA X X L V V V V V V X X X X A10 X X L V L H L H L H X X X A11 A9 - A0 X X V V V V V V X X X X X
2.2 DQM Truth Table
FUNCTION Data write/output enable Data mask/output disable Symbol ENB MASK CKE n-1 H H n X X DQM L H
2.3 CKE Truth Table
Current State Activating Any Clock suspend Idle Idle Self refresh Idle Power down Function Clock suspend mode entry Clock suspend Clock suspend mode exit CBR refresh command Self refresh entry Self refresh exit Power down entry Power down exit Symbol CKE n-1 H L L H H L L H L n L L H H L H H L H CS X X X L L L H X X RAS X X X L L H X X X CAS X X X L L H X X X WE X X X H H H X X X Address X X X X X X X X X
REF SELF
H : High level, L : Low level X : High or Low level (Don't care), V : Valid Data input
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
2.4 Operative Command Table (note 1)
Current state Idle CS H L L L L L L L H L L L L L L L H L L L L L L L L H L L L L L L L L RAS X H H H L L L L X H H H L L L L X H H H H L L L L X H H H H L L L L CAS X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L WE X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L Address X X BA, CA, A10 BA, CA, A10 BR, RA BA, A10 X Op-Code X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code Command DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MPS DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Action Nop or Power down Nop or Power down ILLEGAL ILLEGAL Row active Nop Refresh or Self refresh Mode register access Nop Nop Begin read : Determine AP Begin write : Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to endRow active Continue burst to endRow active Burst stopRow active Term burst, new read : Determine AP Term burst, start write : Determine AP ILLEGAL Term burst, precharging ILLEGAL ILLEGAL Continue burst to endwrite recovering Continue burst to endwrite recovering Burst stopRow active Term burst, start read : Determine AP Term burst, new write : Determine AP ILLEGAL Term burst, precharging ILLEGAL ILLEGAL Notes 2 2 3 3
4
Row active
5 5 3 6
Read
7 7,8 3
write
7,8 7 3 9
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Current state Read with auto precharge
Write with auto precharge
CS H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L
RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L
CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L
WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L
Address X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op - Code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op - code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op - Code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op - Code
Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL PEF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS
Action Continue burst to endPrecharging Continue burst to endPrecharging ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to endwrite recovering with auto precharge Continue burst to endwrite recovering with auto precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NopEnter idle after tRP NopEnter idle after tRP NopEnter idle after tRP ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRP ILLEGAL ILLEGAL NopEnter row active after tRCD NopEnter row active after tRCD NopEnter row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Notes
11 11 3,11 3,11
11 11 3,11 3,11
Precharging
3 3 3
Row activating
3 3 3, 9 3
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Current state Write recovering
Write recovering with auto precharge
Auto Refreshing
Mode register setting
CS H L L L L L L L L H L L L L L L L L H L L L L H L L L L
RAS X H H H H L L L L X H H H H L L L L X H H L L X H H H L
CAS X H H L L H H L L X H H L L H H L L X H L H L X H H L X
WE X H L H L H L H L X H L H L H L H L X X X X X X H L X X
Address X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op - Code X X X BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op - Code X X X X X X X X X X
Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL PEF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP/BST READ/WRIT ACT/PRE/PALL REF/SELF/MRS DESL NOP BST READ/WRITE ACT/PRE/PALL/ REF/SELF/MRS
Action NopEnter row active after tDPL NopEnter row active after tDPL NopEnter row active after tDPL Start read, Determine AP New write, Determine AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL NopEnter precharge after tDPL NopEnter precharge after tDPL NopEnter precharge after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NopEnter idle after tRC NopEnter idle after tRC ILLEGAL ILLEGAL ILLEGAL NopEnter idle after 2 Clocks NopEnter idle after 2 Clocks ILLEGAL ILLEGAL ILLEGAL
Notes
8 3 3
3,8,11 3,11 3,11 3
Note 1. All entries assume that CKE was active (High level) during the preceding clock cycle. 2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power downmode. All input buffers except CKE will be disabled. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address(BA), depending on the state of that bank. 4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode. All input buffers except CKE will be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Must mask preceding data which don't satisfy tDPL. 10. Illegal if tRRD is not satisfied. 11. Illegal for single bank, bur legal for other banks in multi-bank devices.
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
2.5 Command Truth Table for CKE (Note 1)
Current state Self refresh (S.R.) CKE n-1 H L L L L L H H H H H H H H L L H L L H H H H H H H H H H L H H L L CKE n X H H H H L H H H H L L L L H L X H L H H H H H L L L L L X H L H L CS X H L L L X H L L L H L L L X X X X X H L L L L H L L L L X X X X X RAS X X H H L X X H H L X H H L X X X X X X H L L L X H L L L X X X X X CAS X X H L X X X H L X X H L X X X X X X X X H L L X X H L L X X X X X WE X X X X X X X X X X X X X X X X X X X X X X H L X X X H L X X X X X X Op - Code X X X X X X Op - Code Address X X X X X X X X X X X X X X X X X X Action INVALID, CLK (n - 1)would exit S.R. S.R. Recovery S.R. Recovery ILLEGAL ILLEGAL Maintain S.R. Idle after tRC Idle after tRC ILLEGAL ILLEGAL Begin clock suspend next cycle Begin clock suspend next cycle ILLEGAL ILLEGAL Exit clock suspend next cycle Maintain clock suspend INVALID, CLK (n - 1) would exit P.D. EXIT P.D. Idle Maintain power down mode Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operation in Operative Command Table Auto Refresh Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Self refresh Refer to operations in Operative Command Table Power down Refer to operations in Operative Command Table Begin clock suspend next cycle Exit clock suspend next cycle Maintain clock suspend Notes
2 2
Self refresh recovery
5 5
2
Power down (P.D.) Both banks idle
2
3
3
Any state other than listed above
4
1. 2. 3. 4. 5.
H : High level, L : low level, X : High or low level (Don't care). CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. Power down and Self refresh can be entered only from the both banks idle state. Must be legal command as defined in Operative Command Table. Illegal if tSREX is not satisfied.
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
3.Initiallization
Before starting normal operation, the following power on sequence is necessary to prevent SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high , DQN high and NOP condition at the inputs. 2. Maintain stable power, table clock , and NOP input conditions for a minimum of 200us. 3. Issue precharge commands for all bank. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is in idle state and ready for normal operation.
4.Programming the Mode Register
The mode register is programmed by the mode register set command using address bits BA0,BA1,A11 through A0 as data inputs. The register retains data until it is reprogrammed or the device loses power. The mode register has four fields; Options CAS latency Wrap type Burst length : BA0,BA1,A11 through A7 : A6 through A4 : A3 : A2 through A0
Following mode register programming, no command can be asserted before at least two clock cycles have elapsed. CAS Latency CAS latency is the most critical parameter being set. It tells the device how many clocks must elapse before the data will be available. The value is determined by the frequency of the clock and the speed grade of the device. The value can be programmed as 2 or 3. Burst Length Burst Length is the number of words that will be output or input in read or write cycle. After a read burst is completed, the output bus will become high impedance. The burst length is programmable as 1, 2, 4, 8 or full page. Wrap Type (Burst Sequence) The wrap type specifies the order in which the burst data will be addressed. The order is programmable as either "Sequential" or "Interleave". The method chosen will depend on the type of CPU in the system.
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
5.Mode Register
BA0 0 BA0 x BA0 0 BA1 0 BA1 x BA1 0 11 0 11 x 11 0 10 0 10 x 10 0 9 0 9 1 9 0 8 0 8 0 8 0 7 1 7 0 7 1 6 5 4 3 3 WT 3 WT 2 2 1 0 JEDEC Standard Test Set 654 LTMODE 654 LTMODE 10 BL 210 BL Burst Read and Single Write (for Write Through Cache) Burst Read and Single Write Bits2 - 0 000 001 010 011 100 101 110 111 0 1 x = Don't care WT = 0 1 2 4 8 R R R Fullpage WT = 1 1 2 4 8 R R R R
Burst length
Wrap type
Sequential Interleave
Bits 6-4 000 001 010 011 100 101 110 111
Latency mode
CAS latency R R 2 3 R R R R
Remark R : Reserved
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
5.1 Burst Length and Sequence
(Burst of Two)
Starting Address (column address A0, binary) (decimal) 0 1 (Burst of Four) Starting Address (column address A1 - A0, binary) 00 01 10 11 (Burst of Eight) Starting Address (column address A2 - A0, binary) (decimal) 000 001 010 011 100 101 110 111 Sequential Addressing Sequence (decimal) 0, 1 1, 0 Interleave Addressing Sequence
0, 1 1, 0
Sequential Addressing Sequence (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2
Interleave Addressing Sequence (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0
Sequential Addressing Sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1 ,2 4, 5, 6, 7, 0, 1, 2, 3 5, 6 ,7, 0, 1, 2, 3, 4 6, 7 ,0 ,1 ,2 ,3 ,4 ,5 7, 0, 1, 2, 3, 4, 5, 6
Interleave Addressing Sequence
0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length being 256 for 4Mx16.
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
6.Address Bits of Bank-Select and Precharge
Row A0 A1 A2 (Activate command) A3 A4 A5 A6 A7 A8 A9 A10 A11 BA1 BA0 BA1 0 0 1 1 BA0 0 1 0 1 Result Select Bank A "Activate " command Select Bank B "Activate" command Select Bank C "Activate" command Select Bank D "Activate" command
Row A0 A1 A2 (Precharge command)
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA1
BA0 A10 0 0 0 0 1 BA1 0 0 1 1 X BA0 0 1 0 1 X Result Precharge Bank A Precharge Bank B Precharge Bank C Precharge Bank D Precharge All Banks
X : Don't care
0 1
Disables Auto-Precharge (End of Burst) Enables Auto - Precharge (End of Burst)
Row
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA1
BA0
BA1 0 0 1 1
BA0 0 1 0 1
Result Enables Read/Write commands for Bank A Enables Read/Write commands for Bank B Enables Read/Write commands for Bank C Enables Read/Write commands for Bank D
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
7.Precharge
The precharge command can be asserted anytime after tRAS(min.) is satisfied. Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters the idle state after tRP(min.) is satisfied. The parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as follows.
T0 CLK Command Read
T1
T2
T3
T4
T5
T6
Burst lengh=4 T7
PRE CAS latency = 2 DQ Q0 Q1 Q2 Q3 Hi - Z
Command CAS latency = 3 DQ
Read
PRE
Hi - Z Q0 Q1 Q2 Q3
(t R AS is satisfied)
In order to write all data to the memory cell correctly, the asynchronous parameter "tDPL" must be satisfied. The tDPL(min.) specification defines the earliest time that a precharge command can be asserted. The minimum number of clocks can be calculated by dividing tDPL(min.) with the clock cycle time. In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is valid. In the following table, minus means clocks before the reference; plus means time after the reference. CAS latency 2 3 Read -1 -2 Write + tDPL(min.) + tDPL(min.)
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
8.Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. If A10 is high in the read or write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and begins automatically. In the write cycle, tDAL(min.) must be satisfied before asserting the next activate command to the bank being precharged. When using auto precharge in the read cycle, knowing when the precharge starts is important because the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. Once auto precharge has started, an activate command to the bank can be asserted after tRP has been satisfied. A Read or Write command without auto - precharge can be terminated in the midst of a burst operation. However, a Read or Write command with auto - precharge can not be interrupted by the same bank commands before the entire burst operation is completed. Therefore use of the same bank Read, Write, Precharge or Burst Stop command is prohibited during a read or write cycle with auto - precharge. It should be noted that the device will not respond to the Auto - Precharge command if the device is programmed for full page burst read or write cycles. The timing when the auto precharge cycle begins depends both on both the CAS Iatency programmed into the mode register and whether the cycle is read or write. 8.1 Read with Auto Precharge During a READA cycle, the auto precharge begins one clock earlier (CL = 2) or two clocks earlier (CL = 3) than the last word output. READ with AUTO PRECHARGE
Burst lengh = 4 T0 T1 T2 T3
T4
T5
T6
T7
T8
CLK No New Command to Bank B Command
READA B
Auto precharge starts
CAS latency = 2 D Q QB0 QB1 QB2 QB3 Hi - Z
No New Command to Bank B Auto precharge starts Command CAS latency = 3 D Q QB0 QB1 QB2 QB3 H-Z i
READA B
Remark READA means READ with AUTO PRECHARGE
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
8.2 Write with Auto Precharge
During a write cycle, the auto precharge starts at the timing that is equal to the value of tDPL(min.) after the last data word input to the device.
WRITE with AUTO PRECHRGE
Burst lengh = 4 T0 CLK Command
WRITA B
T1
T2
T3
T4
T5
T6
T7
T8
AUTO PRECHARGE starts
CAS latency = 2 DQ
DB0 DB1 DB2
t
DPL
DB3
Hi - Z_
Command CAS latency = 3 DQ
AUTO PRECHARGE starts
WRITA B
tDPL
Hi - Z
DB0
DB1
DB2
DB3
Remark WRITA means WRITE with AUTO Precharge
In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference; plus means clocks after the reference.
CAS latency 2 3
Read -1 -2
Write + tDPL(min.) + tDPL(min.)
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
9. Read / Write Command Interval
9.1 Read to Read Command Interval During a read cycle when a new read command is asserted, it will be effective after the CAS latency, even if the previous read operation has not completed. READ will be interrupted by another READ. Each read command can be asserted in every clock without any restriction.
READ to READ Command Interval
Burst lengh=4, CAS latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK Command Read A Read B
DQ
Q A0
QB0
QB1
QB2
Q B3
Hi-Z_
1 cycle
9.2 Write to Write Command Interval During a write cycle, when a new Write command is asserted,the previous burst will terminated and the new burst will begin with a new write command. WRITE will be interrupted by another WRITE. Each write command can be asserted in every clock without any restriction.
WRITE to WRITE Command Interval
Burst lengh=4, CAS latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK Command Write A Write B
DQ
QA0
Q B0
QB1
QB2
Q B3
Hi-Z_
1 cycle
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
9.3 Write to Read Command Interval The write command to read command interval is also a minimum of 1 cycle. Only the write data before the read command will be written. The data bus must be Hi-Z at least one cycle prior to the first DOUT. WRITE to READ Command Interval
Burst lengh=4 T0 T1 T2 T3 T4 T5 T6 T7 T8
CLK 1 cycle Command CAS latency=2 DA0 Hi-Z WRITE A Read B
DQ
QB0
QB1
Q B2
Q B3
Command
Write A
Read B
CAS latency=3 DQ DA0 Hi-Z QB0 Q B1 Q B2 QB3
9.4 Read to Write Command Interval During a read cycle, READ can be interrupted by WRITE. DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data conflict. The data bus must be Hi-Z using DQM before Write.
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
READ to WRITE Command Interval
C S lae c = A tny 2 T0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8
CK L
Cm ad o mn
Ra ed
W rite
DM Q
D Q
H i-Z
D 0
D 1
D 2
D 3
1 cycle
T 0
T 1
T 2
T 3
T 4
T 5
T 6
T7
B r tle gh 8 C Slaten y 2 us n t = , A c= T8 T 9
CK L
Cm a d o mn
Ra ed
W ie rt
DM Q
D Q
Q 0
Q 1
Q 2 H- i i Zs n c s ay ees r
D 0
D 1
D 2
e a p : Burst length=4, C Slae c = x m le A tny 3 T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 T8
CK L
C omm and
Ra ed
W rite
DM Q
D Q Q 2 H is i-Z necessary D 0 D 1 D 2
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
10.BURST Termination
There are two methods to terminate a burst operation other than using a read or a write command. One is the burst stop command and the other is the precharge command. 10.1 BURST Stop Command During a read burst, when the burst stop command is issued, the burst read data are terminated and the data bus goes to highimpedance after the CAS latency from the burst stop command. During a write burst, when the burst stop command is issued, the burst write data are terminated and data bus goes to Hi-Z at the same clock with the burst stop command. Burst Termination
Burst lengh=X, C SIntency=2,3 A T0 T1 T2 T 3 T4 T 5 T 6 T 7
CK L
Cm ad o mn
Read
BT S
CAS latency=2 D Q
Q0
Q1
Q2
H i-Z
CAS latency=3 D Q
Q 0
Q 1
Q 2
Hi-Z
Remark BST: Burst stop command
Burst lengh=X, C S laten A cy=2 ,3 T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7
CK L
C m and om
Write
BT S
CASlatency=2,3 Q 0 D Q Q0 Q 1 Q 2 Hi-Z_
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
10.2 PRECHARGE TERMINATION
10.2.1 PRECHARGE TERMINATION in READ Cycle During READ cycle, the burst read operation is terminated by a precharge command. When the precharge command is issued, the burst read operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. When CAS latency is 2, the read data will remain valid until one clock after the precharge command. When CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Precharge Termination in READ Cycle
T0
T1
T2
T3
T4
T5
T6
T7
Burst lengh= X T8
CLK
Command
Read
PRE tR P
ACT
CAS latency=2 DQ Q0 Q1 Q2 Q3 Hi-Z
command
Read
PRE tR P
ACT
C A S latency=3 DQ
Q0
Q1
Q2
Q3
Hi-Z
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
10.2.2 Precharge Termination in WRITE Cycle
During WRITE cycle, the burst write operation is terminated by a precharge command. When the precharge command is issued, the burst write operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. The DQM must be high to mask invalid data in. During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same clock as the precharge command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
T0 CLK C ommand CAS latency = 2 DQM DQ D 0 Write
T1
T2
T3
T4
T5
T6
T7
Burst lengh = X T8
PRE
ACT
D1
D2
D3
D 4 tRP
Hi - Z
command CASlatency = 3
DQM
Write
PRE
ACT
DQ
D0
D1
D2
D 3
D4
Hi - Z tRP
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Timing Diagram
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Mode Register Set
T0 CLK
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CKE
tRSC
CS
RAS
CAS
WE
BA0,1
A10
Address Key
ADD
DQM
tRP
DQ
Hi-Z
Precharg Comman All Banks
Mode Set Comman
Comman
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
AC Parameters for Write Timing (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 T2 T3
T4 T5 T6 T7 T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CL t CH t t tCKS CMS t CMH CK2 Begin Auto Precharge Bank A Begin Auto Precharge Bank B
CKE
t
CKH
CS
RAS
CAS
WE
*BA0
A10
tAS t AH
ADD
DQM
t RCD t RRD t RC t DAL t DS t t DH DPL t RP
DQ
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3
Activate Write with Command Auto Precharge Bank A Command Bank A
Write with Activate Activate Command Auto Precharge Command Command Bank B Bank A Bank B
Write without Auto Precharge Command Bank A
Precharge Command Bank A
Activate Command Bank A
Activate Command Bank B
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
AC Parameters for Write Timing (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2
T3 T4 T5
T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CLK
t CL t CH t CMS t tCK3 Begin Auto Precharge Bank A Begin Auto Precharge Bank B
CKE
t CKS
t CKH
CMH
CS
RAS
CAS
WE
*BA0
A10
t AS t AH
ADD
DQM
tRCD
DQ
t
RRD RC
tDAL
t DS t t DH DPL t RP
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3
QAb0 QAb1 QAb2 QAb3
Activate Command Bank A
Write with Auto Precharge Command Bank A
Activate Command Bank B
Write with Auto Precharge Command Bank B
Activate Command Bank A
Write without Auto Precharge Command Bank A
Precharge Command Bank A
Activate Command Bank A
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
AC Parameters for Read Timing (1 of 2)
Burst Length=2, CAS Latency=2
T0 CLK
tCH tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
tCK2 tCMS t CMH Begin Auto Precharge Bank B t CKH
CKE
tCKS
CS
RAS
CAS
WE
*BA0
A10
t AS tAH
ADD
tRRD t RAS tRC
DQM
tAC2 tLZ t AC2 tOH QAa0
t RCD
t HZ tOH QAa1 QBa0
t RP tHZ QBa1
DQ
Hi-Z
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read with Auto Precharge Command Bank B
Precharge Command Bank A
Activate Command Bank A
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
AC Parameters for Read Timing (2 of 2)
Burst Length=2, CAS Latency=3 T0 CLK
t CH t CL t CK3 tCMS tCMH Begin Auto Precharge Bank B
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
CKE
t CKS
t
CKH
CS
RAS
CAS
WE
*BA0
A10
t AH t AS
ADD
t RRD t RAS t RC t RP
DQM
t RCD
tAC3 tLZ
t AC3 tOH
t HZ tOH
QAa1 QBa0
t
HZ
DQ
Hi-Z
QAa0
QBa1
Activate Command Bank A
Read Command Bank A
Activate Command Bank B
Read with Auto Precharge Command Bank B
Precharge Command Bank A
Activate Command Bank A
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Power on Sequence and Auto Refresh (CBR)
T0 T1 T2 CLK CKE
T3 T4 T5
T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
High level is required
t RSC Minimum of 8 Refresh Cycles are required
CS
RAS
CAS
WE
BA0, 1
A10
Address Key
ADD
DQM
High Level is Necessary t t
RP
DQ
Hi-Z
RC
Precharge Inputs Command All Banks must be stable for 200us
1st Auto Refresh Command
2nd Auto Refresh Command
Mode Register Set Command
Command
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Clock Suspension During Burst Read (Using CKE)(1 of 2)
Burst Length=4, CAS Latency=2
T0 CLK
t
T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CK2
CKE
CS
RAS
CAS
WE
*BA0
A10
RAa
ADD
RAa
CAa
DQM
t HZ
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3
Activate Command Bank A
Read Command Bank A
Clock Suspended 1 Cycle
Clock Suspended 2 Cycles
Clock Suspended 3 Cycles
*BA1="L" , Bank C , D = Idle
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Clock Suspension During Burst Read (Using CKE)(2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 CLK
t CK3
T2 T3 T4
T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BA0
A10
RAa
ADD
RAa
CAa
DQM
t HZ
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3
Activate Command Bank A
Read Command Bank A
Clock Suspended 1 Cycles
Clock Suspended 2 Cycles
Clock Suspended 3 Cycles
*BA1="L" , Bank C , D = Idle
G-Link Technology Corporation,Taiwan
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Clock Suspension During Burst Write (Using CKE)(1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 CLK
t CK2
T2 T3
T4 T5 T6
T7 T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BA0
A10
RAa
ADD
RAa
CAa
DQM
DQ
Hi-Z
DAa0 DAa1
DAa2
DAa3
Activate Command Bank A
Clock Suspended 1 Cycle Write Command Bank A
Clock Suspended 2 Cycles
Clock Suspended 3 Cycles
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 37 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Clock Suspension During Burst Write (Using CKE)(2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 CLK
t CK3
T2 T3
T4 T5 T6
T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BA0
A10
RAa
ADD
RAa
CAa
DQM
DQ
Hi-Z
DAa0 DAa1 DAa2 DAa3
Activate Command Bank A
Clock Suspended 1 Cycle Write Command Bank A
Clock Suspended 2 Cycles
Clock Suspended 3 Cycles
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 38 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Power Down Mode and Clock Mask
Burst Length=4, CAS Latency=2
T0 CLK
t
T1 T2 T3 T4
T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CK2
t t CKS
CKH
t
CKS
CKE
VALID
CS
RAS
CAS
WE
*BA0
A10
RAa
ADD
RAa
CAa
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3
Activate Command Bank A
ACTIVE STANDBY
Read Command Bank A Clock Mask Start Clock Mask End
Precharge Command Power Down Mode Entry
Precharge Standby
Power Down Mode Exit
Power Down Mode Entry
Power Down Mode Exit
Command
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 39 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Auto Refresh (CBR)
Burst Length=4, CAS Latency=2 T0 T1 CLK
t CK2
T2 T3
T4 T5 T6 T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BA0, 1
A10
RAa
ADD
RAa
CAa
DQM
t RP t RC t RC
Q0 Q1 Q2 Q3
DQ
Hi-Z
Precharge CBR Refresh Command Command All Banks
CBR Refresh Command
Activate Read CommandCommand
*BA1="L" , Bank C , D = Idle
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 40 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Self Refresh (Entry and Exit)
CLK can be Stopped
T0 T1 CLK
T2 T3
T4 T5
** T6 T7 T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t SRX
t
SRX
t CKS
CKE
t CKS
CS
RAS
CAS
WE
*BA0
A10
ADD
t RC t
DQM
RC
DQ
Hi-Z
All Banks must be idle
Self refresh Entry
Self Refresh Exit
Self Refresh Entry
Self Refresh Exit
Activate Command
*BA1="L" , Bank C , D = Idle *Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles before CKE=High
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 41 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Random Column Read (Page With Same Bank)(1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 CLK
t CK2
T2 T3
T4 T5 T6 T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BA0
A10
RAa
RAd RAa
ADD
RAa
CAa
CAb
CAc
RAd
CAd
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3
QAd0 QAd1 QAd2 QAd3
Precharge Read Command Command Bank A Bank A
Read Read Command Command Bank A Bank A
Precharge Activate Read Command Command Command Bank A Bank A Bank A
*BA1="L" , Bank C , D = Idle
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 42 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Random Column Read (Page With Same Bank)(2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 CLK
t CK3
T2 T3
T4 T5
T6 T7 T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BA0
A10
RAa
RAd
ADD
RAa
CAa
CAb
CAc
RAd
CAd
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3
Activate Command Bank A
Read Command Bank A
Read Read Command Command Bank A Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 43 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Random Column Write (Page With Same Bank)(1 of 2)
Burst Length=4, CAS Latency=2
T0 CLK
T1 T2 T3
T4 T5
T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE
CS
RAS
CAS
WE
*BA0
A10
Ra
Rd
ADD
Ra
Ca
Cb
Cc
Rd
Cd
DQM
DQ
Hi-Z
Da0
Da1 Da2 Da3
Db0 Db1
Dc0 Dc1
Dc2 Dc3
Dd0 Dd1 Dd2
Dd3
Activate Command Bank B
Write Command Bank B
Write Write Command Command Bank B Bank B
Precharge Activate Write Command Command Command Bank B Bank B Bank B
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 44 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Random Column Write (Page With Same Bank)(2 of 2)
Burst Length=4, CAS Latency=3
T0 CLK
T1 T2 T3
T4 T5
T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK
CKE
CS
RAS
CAS
WE
*BA0
A10
Ra
Rd
ADD
Ra
Ca
Cb
Cc
Rd
Cd
DQM
DQ
Hi-Z
Da0
Da1 Da2 Da3
Db0 Db1 Dc0 Dc1
Dc2 Dc3
Dd0 Dd1
Activate Command Bank B
Write Command Bank B
Write Write Command Command Bank B Bank B
Precharge Command Bank B
Activate Command Bank B
Write Command Bank B
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 45 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Random Row Read (Interleaving Banks)(1 of 2)
Burst Length=8, CAS Latency=2
T0 T1 T2 T3 CLK
t CK2
T4 T5
T6 T7 T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
*BA0
A10
ADD
t AC2 t RP
DQM
t RCD
DQ
Hi-Z
QBa0 QBa1 QBa2QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5QAa6 QAa7
QBb0 QBb1
Activate Read Command Command Bank B Bank B
Activate Command Bank A
Precharge Active Command Command Bank B Bank B Read Command Bank A
Read Command Bank B
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 46 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Random Row Read (Interleaving Banks)(2 of 2)
Burs tLength=8, CAS Latency=3
T0 T1 T2
T3 T4
T5 T6
T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
High
CS
RAS
CAS
WE
*BA0
A10
ADD
t RCD t AC3 t
DQM
RP
DQ
Hi-Z
QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5QAa6 QAa7 QBb0
Activate Command Bank B
Read Command Bank B
Activate Command Bank A
Precharge Read Command Command Bank B Bank A
Activate Command Bank B
Read Precharge Command Command Bank B Bank A
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 47 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Random Row Write (Interleaving Banks)(1 of 2)
Burst Length=8, CAS Latency=2
T0
T1 T2 T3
T4 T5
T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
High
CS
RAS
CAS
WE
*BA0
A10
ADD
DQM
t
RCD
t
DPL
t
RP
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAb0QAb1 QAb2 QAb3 QAb4
Activate Write Command Command Bank A Bank A
Activate Command Bank B
Precharge Active Command Command Bank A Bank A Write Command Bank B
Write Command Bank A Precharge Command Bank B
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 48 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Random Row Write (Interleaving Banks)(2 of 2)
Burst Length=8, CAS Latency=3
T0 T1 CLK
t CK
T2 T3
T4 T5 T6
T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
*BA0
A10
ADD
RBa
DQM
t DPL
t RP
t DPL
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBb7QAb0 QAb1 QAb2 QAb3
Activate Command Bank A
Write Command Bank A
Activate Command Bank B
Precharge Write Command Command Bank A Bank B
Activate Command Bank A
Precharge Write Command Command Bank A Bank B
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 49 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Read and Write Cycle (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 CLK
t CK2
T2 T3
T4 T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BA0
A10
RAa
ADD
RAa
CAa
CAb
CAc
DQM
Hi-Z
DQ
QAa0 QAa1 QAa2 QAa3
DAb0 DAb1
DAb3
QAc0 QAc1
QAc3
Activate Write Command Command Bank A Bank A
Write The Write Data Command is Masked with a Bank A Zero Clock latency
Read Command Bank A
The Read Data is Masked with Two Clocks Latency
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 50 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Read and Write Cycle (2 of 2)
Burst Length=4, CAS Latency=3
T0
T1 T2 T3
T4 T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
*BA0
A10
RAa
ADD
RAa
CAa
CAb
CAc
DQM
Hi-Z
DQ
QAa0 QAa1 QAa2QAa3
DAb0 DAb1
DAb3
QAc0 QAc1
QAc3
Activate Command Bank A
Read Command Bank A
Write The Write Read Commandis Masked with a Command Bank A Bank A
Zero Latency
The Read Data is Masked with Two Clock Latency
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 51 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Interleaved Column Read Cycle (1 of 2)
Burst Length=4, CAS Latency=2
T0 CLK
T1 T2 T3
T4 T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t CK2
CKE
CS
RAS
CAS
WE
*BA0
A10
Ra
Ra
ADD
Ra
Cb
Ra
Ca
Cb
Cc
Cb
Cd
DQM
t RCD
t AC2
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QBd0 QBd1 QBd2 QBd3
Activate Read Activate Read Read Read Read Read Command Command CommandCommand CommandCommandCommand Command Bank A Bank B Bank B Bank A Bank B Bank B Bank A Bank B Precharge Command Bank A
Precharge Command Bank B
*BA1="L" , Bank C , D = Idle
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 52 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Interleaved Column Read Cycle (2 of 2)
Burst Length=4, CAS Latency=3
T0
T1 T2 T3 T4 T5
T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
*BA0
A10
Ra
Ra
ADD
Ra
Ca
Ra
Ca
Cb
Cc
Cb
DQM
t t RCD RRD
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QAb2 QAb3
t
AC3
DQ
Hi-Z
Activate Command Bank A
Read Command Bank A Activate Command Bank B
Read Read Read Read Command Command Command Command Bank B Bank B Bank B Bank A
Precharge Command Bank B
Precharge Command Bank A
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 53 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Interleaved Column Write Cycle (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1 CLK
t CK2
T2 T3 T4
T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BA0
A10
Ra
Ra
ADD
Ra
Ca
Ra
Ca
Cb
Cc
Cb
Cb
DQM
t RCD t RRD
t RP
t DPL
DQ
Hi-Z
DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBb0 DBb1 DBc0 DBc1 DAb0 DAb1 DBd0 DBd1 DBd2DBd3
Activate Write Write Write Write Write Activate Command Command Command Command CommandCommandCommand Bank B Bank A Bank B Bank B Bank A Bank A Bank B
Precharge Command Bank A Write Command Bank B
Precharge Command Bank B
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 54 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Interleaved Column Write Cycle (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
CS
RAS
CAS
WE
*BA0
A10
Ra
Ra
ADD
Ra
Ca
Ra
Ca
Cb
Cc
Cb
Cd
t
DQM
t Hi-Z
RCD
t
DPL
t
DPL
RRD
t
RP
DQ
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QBd0 QBd1 QBd2 QBd3
Activate Command Bank A
Write Command Bank A Activate Command Bank B
Write Write Write Write Command Command Command Command Bank B Bank B Bank B Bank A
Write Command Bank B Precharge Command Bank A
Precharge Command Bank B
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 55 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Auto Precharge after Read Burst (1 of 2)
Burst Length=4, CAS Latency=2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B
CKE
High
CS
RAS
CAS
WE
*BA0
A10
Ra
Ra
Rb
Rc
ADD
Ra
Ca
Ra
Ca
Cb
Rb
Cb
Rc
Cc
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2
Activate Command Bank A
Read Command Bank A
Activate Read with Command Auto Precharge Command Bank B Bank B
Read with Auto Precharge Command Bank A
Activate Command Read with Bank A Auto Precharge Command Read with Activate Bank B Auto Precharge Command Command Bank B Bank A
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 56 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Auto Precharge after Read Burst (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 CLK
t CK3
T2 T3 T4 T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
Start Auto Precharge Bank B
Start Auto Precharge Bank A
Start Auto Precharge Bank B
CS
RAS
CAS
WE
*BA0
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Cb
Rb
RBb
Cb
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2
Activate Command Bank A
Activate Command Bank B Read Command Bank A
Read with Auto Precharge Command Bank B
Read with Auto Precharge Command Bank A
Activate Command Bank B
Write with Auto precharge Command Bank B
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 57 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Auto Precharge after Write Burst (1 of 2)
Burst Length=4, CAS Latency=2
T0 T1
T2 T3
T4 T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
High
Start Auto Bank B
Start Auto Bank A
Start Auto Bank B
CS
RAS
CAS
WE
*BA0
A10
Ra
Ra
Rb
Rc
ADD
Ra
Ca
Ra
Ca
Cb
Rb
Cb
Rc
Cc
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3
Activate Write Write with Activate Command Command Command Auto Precharge Bank A Bank A Bank B Command Bank B
*BA1="L" , Bank C , D = Idle
Activate Write with Activate Command Auto Precharge Command Bank A Command Bank B Write with Bank A Auto Precharge Write with Bank A Auto Precharge Command Bank B
Start Auto Precharge Bank A
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 58 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Auto Precharge after Write Burst (2 of 2)
Burst Length=4, CAS Latency=3
T0 T1 T2 T3 CLK
t CK3
T4 T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
Start Auto Precharge Bank B
Start Auto Precharge Bank A
Start Auto Precharge Bank B
CS
RAS
CAS
WE
*BA0
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Cb
Rb
RBb
Cb
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3
Activate Command Bank A
Activate Command Bank B Read Command Bank A
Read with Auto Precharge Command Bank B
Read with Auto Precharge Command Bank A
Activate Command Bank B
Write with Auto precharge Command Bank B
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 59 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Full Page Read Cycle (1 of 2)
Burst Length=Full Page, CAS Latency=2
T0 T1 CLK
t CK2
T2 T3 T4
T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
*BA0
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Rb
DQM
t RP
DQ
Hi-Z
QAa
QAa+1QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+51 QBa+6
Activate Command Bank A
Read Bank A
Activate Bank B
Read Bank B The burst counter from the highest page address back to during this time
Full page burst operation does terminate when the burst length satisfied; the burst increments and continues beginning with the starting
Precharg Activate Command Comman Bank B Bank B Burst Stop Comman
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 60 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Full Page Read Cycle (2 of 2)
Burst Length=Full Page, CAS Latency=3
T0 T1
T2 T3 T4
T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
High
CS
RAS
CAS
WE
*BA0
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Rb
DQM
DQ
Hi-Z
QAa
QAa+1 QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa0 QBa+1 QBa+2QBa+3 QBa+4 QBa+5
Activate Command Bank A
Read Bank A
Activate Bank B
Read Bank B The burst counter from the highest page address back to during this time
Full page burst does not teminate the burst length is the burst counter and continues beginning with the addres
Precharg Command Bank B Burst Stop Comman
Activate Comman Bank B
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 61 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Full Page Write Cycle (1 of 2)
Burst Length=Full Page, CAS Latency=2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
High
CS
RAS
CAS
WE
*BA0
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Rb
DQM
t BDL
DQ
Hi-Z
QAa QAa+1 QAa+2 QAa+3 QAa-1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+5 QBa+6
Activate Command Bank A
Write Command Bank A
Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval
Write Command Bank B
Data is ignored Precharge Command Bank B Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address Burst Stop Command
Activate Command Bank B
*BA1="L" , Bank C , D = Idle
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 62 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Full Page Write Cycle (2 of 2)
Burst Length=Full Page, CAS Latency=3
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK3
CKE
High
CS
RAS
CAS
WE
*BA0
A10
Ra
Ra
Rb
ADD
Ra
Ca
Ra
Ca
Rb
DQM
t Hi-Z
DAa DAa+1 DAa+2 DAa+3 DAa-1 DAa
BDL
Data is ignored.
DQ
DAa+1
DBa
DBa+1
DBa+2 DBa+3
DBa+4
DBa+5
Activate Command Bank A
Write Command Bank A
Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval
Write Command Bank B Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address
Precharge Command Bank B Burst Stop Command
Activate Command Bank B
*BA1="L" , Bank C , D = Idle
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
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G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Burst Read and Single Write Operation
Burst Length=4, CAS Latency=2
T0
T1 T2
T3
T4
T5
T6
T7
T8
T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t
CK2
CKE
High
CS
RAS
CAS
WE
*BA0
A10
RAa
ADD
RAa
CAa
CAb
CAc
CAd
CAe
DQM
Hi-Z
DQ
Activate Command Bank A
Read Command Bank A
Single Write Command Bank A
Single Write Command Bank A
Read Command Bank A
DQs are masked
Single Write Command Bank A
DQs are masked
*BA1="L" , Bank C , D = Idle
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 64 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Full Page Random Column Read
Burst Length=Full Page, CAS Latency=2
T0 T1 CLK
t CK2
T2 T3 T4
T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
BA
A10
Ra
Ra
Rb
ADD
Ra
Ra
Ca
Ca
Cb
Cb
Cc
Cc
Rb
t RP
DQM DQ
Hi-Z
QAa0 QBa0 QAb0 QAb1 QBb0 QBb1 QAc0 QAc1 QAc2 QBc0 QBc1 QBc2
Activate Activate Command Bank A Bank B Read
Read Bank B Read Bank A
Read Bank B
Read Bank A
Read Bank B
Precharg Command Bank (Bank D) (Precharge Activate Comman Bank B
Bank A
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 65 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Full Page Random Column Write
Burst Length=Full Page, CAS Latency=2
T0 T1 T2 T3 CLK
t CK2
T4 T5 T6
T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
CS
RAS
CAS
WE
*BA0
A10
Ra
Ra
Rb
ADD
Ra
Ra
Ca
Ca
Cb
Cb
Cc
Cc
Rb
t RP
DQM
DQ
Hi-Z
QAa0 QBa0 QAb0 QAb1 QBb0 QBb1 QAc0 QAc1 QAc2 QBc0 QBc1 QBc2
Activate Command Bank A
Activate Command Bank B
Write Command Bank B Write Command Bank A
Write Command Bank B
Write Command Bank A
Write Command Bank B
Precharge Command Bank B (Bank D) (Precharge Termination) Write Data is masked Activate Command Bank B
Write Command Bank A
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 66 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Precharge Termination of a Burst (1 of 2)
Burst Length=8, CAS Latency=2
T0 T1 T2
T3 T4 T5
T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
t CK2
CKE
High
CS
RAS
CAS
WE
*BA0
A10
RAa
RAb
RAc
ADD
RAa
CAa
RAb
CAb
RAc
CAc
t
DPL
t
RP
t
RP
t
RP
DQM
DQ
Hi-Z
QAa0 QAa1 QAa2 Da3 QAb0 QAb1 QAb2 QAc0 QAc1 QAc2
Activate Command Bank A
Write Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Activate Command Bank A
Read Command Bank A
Precharge Command Bank A
Precharge Termination of a Write Burst. Write data is masked.
Precharge Termination of a Read Burst.
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 67 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Precharge Termination of a Burst (2 of 2)
Burst Length=8, CAS Latency=3
T0 T1 CLK
t CK3
T2 T3 T4
T5 T6 T7
T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CKE
High
CS
RAS
CAS
WE
*BA0
A10
RAa
RAb
RAc
ADD
RAa
CAa
RAb
CAb
RAc
t DPL
t RP
t
RAS
t RP
DQM
t RCD
DQ
Hi-Z
DAa0
DAa1
QAb0 QAb1 QAb2 QAb3
Activate Command Bank A
Write
Bank A Bank A Write Data Precharge is of a Write Burst.
Precharg Comman Bank A
Activate
Read Bank A
Activate Bank A Precharge of a Read
Activate Comman Bank A
*BA1="L" , Bank C , D = Idle G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 68 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Ordering information Part Number GLT5640L16 - 5.5TC GLT5640L16 - 6TC GLT5640L16 - 7TC GLT5640L16 - 8TC GLT5640L16 - 10TC GLT5640L16P - 5.5TC GLT5640L16P - 6TC GLT5640L16P - 7TC GLT5640L16P - 8TC GLT5640L16P - 10TC GLT5640L16L - 5.5TC GLT5640L16L - 6TC GLT5640L16L - 7TC GLT5640L16L - 8TC GLT5640L16L - 10TC Cycle time 5.5 ns 6 ns 7 ns 8 ns 10 ns 5.5 ns 6 ns 7 ns 8 ns 10 ns 5.5 ns 6 ns 7 ns 8 ns 10 ns Package
400mil, 54-Pin Plastic TSOP
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 69 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Parts Numbers (Top Mark) Definition :
GLT 5 640 L 16
4 : DRAM 5 : Synchronous DRAM 6 : Standard SRAM /Pseudo SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM 9 : SGRAM
P
SPEED -SRAM
- 7 TC
PACKAGE
T : PDIP(300mil) TS : TSOP(Type I) ST : sTSOP(Type I) TC : TSOPll (40/44) PL : PLCC FA : 300mil SOP FB : 330mil SOP FC : 445mil SOP J3 : 300mil SOJ J4 : 400mil SOJ P : PDIP(600mil) Q : PQFP TQ : TQFP FG : 48Pin BGA 9x12 FH : 48Pin BGA 8x10 FI : 48Pin BGA 6x8 FJ : 60Ball VFBGA
-SRAM
064 : 64K 256 : 256K 512 : 512K 100 : 1M 200 : 2M 400 : 4M
CONFIG.
04 : x04 08 : x08 16 : x16 32 : x32
-DRAM
10 : 1M(C/EDO) 11 : 1M(C/FPM) 12 : 1M(H/EDO) 13 : 1M(H/FPM) 20 : 2M(EDO) 21 : 2M(FPM) 40 : 4M(EDO) 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) 160 : 16M(EDO) 161 : 16M(FPM) 640 : 64M(EDO) 641 : 64M(FPM)
12 : 12ns 15 : 15ns 20 : 20ns 55 : 55ns 70 : 70ns 85 : 85ns 120 : 120ns
-DRAM VOLTAGE
Blank : 5V L : 3.3V M : 2.5V N : 2.0V 25 : 25ns 28 : 28ns 30 : 30ns 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns 70 : 70ns 80 : 80ns 100 : 100ns SDRAM : 5 : 5ns/200 MHZ 5.5 : 5.5ns/183 MHZ 6 : 6ns/166 MHZ 7 : 7ns/143 MHZ 8 : 8ns/125 MHZ 10 : 10ns/100 MHZ
-SDRAM
40 : 4M 160 : 16M 320 : 32M,4Bank 640 : 64M 1280 : 128M 020 - 2M 160 - 16M 320 - 32M
POWER
Blank : Standard L : Low Power LL : Low Low Power SL : Super Low Power
-PSEUDO SDRAM
Temperature Range
E : Extended Temperature I : Industrial Temperature Blank : Commercial Temperature P : Pb - free part
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 70 -
G -LINK
GLT5640L16
4M X 16 CMOS Synchronous Dynamic RAM
Feb 2004 (Rev.3.3)
Packaging Information
* 400mil, 54-Pin Plastic TSOP
DIM A A1 A2 b b1 c c1 D ZD e E E1 L R R1
MILLIMETERS MIN. --0.05 0.95 0.30 0.30 0.12 0.12 22.09 NOM. ----1.00 --------22.22 0.71 REF. 0.80 BASIC 11.56 10.03 0.40 0.12 0.12 11.76 10.16 0.50 ----11.96 10.29 0.60 0.25 --0.455 0.395 0.016 0.005 0.005 MAX. 1.20 0.15 1.05 0.45 0.40 0.21 0.16 22.35 MIN. --0.002 0.037 0.012 0.012 0.005 0.005 0.870
INCHES NOM. ----0.039 --------0.875 0.028 REF. 0.0315 BASIC 0.463 0.400 0.020 ----0.471 0.405 0.024 0.010 --MAX. 0.047 0.006 0.041 0.018 0.016 0.008 0.006 0.880 b b1 E1 A1 L
RAD R1
54
28
A2
RAD R
B B
c
DETAIL A
0X~8X
SECTION B-B
1
D
27
c1 c
BASE METAL WITH PLATING
NOTE: 1. CONTROLLING DIMENSION : MILLIMETERS 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15mm(0.006") PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25mm(0.01") PER SIDE. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm. DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER THAN THE MIN b DIMENSION BY MORE THAN 0.07mm. b
ZD A
DETAIL A
e SEATING PLANE 0.100(0.004")
E
G-Link Technology Corporation,Taiwan
Web : www.glink.com.tw Email : sales@glink.com.tw TEL : 886-2-27968078
- 71 -

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